Track 1 · Writing now · Tentative Q4 2026
Compiler Internals, Memory Anatomy & Optimization Forensics
What the compiler and linker actually do to your code, and how to prove it from the disassembly.
All 5 modules in one purchase. 30% off while the track is being written; each module is delivered the day it’s released. A team licence covers 5 engineers at 20% off 5 single licences.
Release emails for Track 1
One email each time a module in this track ships.
Track 1 / Module 1.1
Stack frames & AAPCS calling conventions
How arguments, return values and saved registers move across a call, and why a corrupted stack looks the way it does.
- Status
- Writing now
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹3,499$69
Path
The step-by-step path for this module is published before it’s released.
Every module includesField manual (PDF)Code and register mapsAI prompts for this topic
This module is part of Track 1 and isn’t out yet. Pre-order the track and you get it the day it ships.
All 5 modules in one purchase. 30% off while the track is being written; each module is delivered the day it’s released. A team licence covers 5 engineers at 20% off 5 single licences.
Track 1 / Module 1.2
Strict aliasing & undefined behavior under -O2/-O3
The aliasing and UB rules that let the optimizer delete code that worked at -O0.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹3,499$69
Path
The step-by-step path for this module is published before it’s released.
Every module includesField manual (PDF)Code and register mapsAI prompts for this topic
This module is part of Track 1 and isn’t out yet. Pre-order the track and you get it the day it ships.
All 5 modules in one purchase. 30% off while the track is being written; each module is delivered the day it’s released. A team licence covers 5 engineers at 20% off 5 single licences.
Track 1 / Module 1.3
Custom linker scripts & VMA/LMA address maps
Writing .ld files that place code and data exactly where the silicon needs them, and copying .data from flash at boot.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹3,499$69
Path
The step-by-step path for this module is published before it’s released.
Every module includesField manual (PDF)Code and register mapsAI prompts for this topic
This module is part of Track 1 and isn’t out yet. Pre-order the track and you get it the day it ships.
All 5 modules in one purchase. 30% off while the track is being written; each module is delivered the day it’s released. A team licence covers 5 engineers at 20% off 5 single licences.
Track 1 / Module 1.4
Memory barriers: DMB, DSB, ISB
When the core, the bus and the peripherals see writes in a different order than you wrote them.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹3,499$69
Path
The step-by-step path for this module is published before it’s released.
Every module includesField manual (PDF)Code and register mapsAI prompts for this topic
This module is part of Track 1 and isn’t out yet. Pre-order the track and you get it the day it ships.
All 5 modules in one purchase. 30% off while the track is being written; each module is delivered the day it’s released. A team licence covers 5 engineers at 20% off 5 single licences.
Track 1 / Module 1.5
Disassembly teardown
Reading compiler output line by line to confirm what actually shipped.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹3,499$69
Path
The step-by-step path for this module is published before it’s released.
Every module includesField manual (PDF)Code and register mapsAI prompts for this topic
This module is part of Track 1 and isn’t out yet. Pre-order the track and you get it the day it ships.
All 5 modules in one purchase. 30% off while the track is being written; each module is delivered the day it’s released. A team licence covers 5 engineers at 20% off 5 single licences.